DRA78x 处理器采用 367 焊球、15mm×15mm、0.65mm 焊球间距（0.8mm 间距规则可用于信号）（通过 Channel 阵列 (VCA) 技术实现）、球栅阵列 (FCBGA) 封装。

此架构旨在昨用经济高效的解决方案，为汽车协处理、混合无线电和放大器应用提供高性能并发性 ， 实现 DRA75x（“Jacinto 6 EP”和“Jacinto 6 Ex”）、DRA74x“Jacinto 6”、DRA72x“Jacinto 6 Eco”和 DRA71x“Jacinto 6 Entry”信息娱乐处理器系列的全面可扩展性。

此外， 提供一整套针对 Arm 和 DSP 的开发工具，其中包括 C 语言编译器和一个实现源代码执行可视化的调试接口。

DRA78x Jacinto 6 RSP（无线电音频处理器）系列器件符合 AEC-Q100 标准。

该器件 采用 简化的电源轨映射，这使得低成本电源管理集成电路 (PMIC) 解决方案得以实现。

The DRA78x processor is offered in a 367-ball, 15×15-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel Array (VCA) technology, ball grid array (S-PBGA) package.

The architecture is designed to deliver high-performance concurrencies for automo ve co-processor, hybrid radio and amplifier applica ons in a cost-effec ve solu on, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6", DRA72x "Jacinto 6 Eco", and DRA71x "Jacinto 6 Entry" family of infotainment processors, including voice, HMI, mul media and smartphone projec on mode capabili es.

Addi onally, provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execu on.

The DRA78x Jacinto 6 RSP (Radio Sound Processor) device family is qualified according to the AEC-Q100 standard.

The device features a simplified power supply rail mapping which enables lower cost PMIC solu ons.